The present application claims the benefit of Korean Patent Application No. 2001-29101 filed on May 25, 2001, which is herein fully incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy circuit capable of detecting deterioration by interference of normal memory cell and redundancy memory cell while reducing detection time.
2. Description of the Related Art
FIG. 1 shows a conventional semiconductor memory device having a redundancy circuit with 64M bit capacitance. Referring to FIG. 1, the conventional semiconductor memory device having the redundancy circuit comprises: a memory cell array unit 50 of 64M bit for storing a plurality of data; a redundancy memory cell array unit 52 of 1K for recovering defective cells of the memory cell array unit 50; and a sense amplification and I/O (input/output) control unit(s) 54 for sensing and amplifying read data received from the memory cell array unit 50 or from the redundancy memory cell array unit 52 and then outputting the amplified data to an I/O line or for sensing and amplifying write data received through the I/O line and then outputting the amplified data to the memory cell array unit 50 or to the redundancy memory cell array unit 52.
The conventional semiconductor memory device further comprises: an address buffer unit 10 for receiving address signals A0xcx9cA12 from an external source; a row address counter unit 12 for generating row address counter signals AR less than 0:12 greater than ; a row address buffer unit 14 for receiving the address signals A less than 0:12 greater than  from the address buffer unit 10 and the row address counter signals AR less than 0:12 greater than  from the row address counter unit 12 and generating row address data signals BXB less than 0:12 greater than ; a row predecoder unit 16 for receiving the row address data signals BXB less than 0:12 greater than  from the row address buffer unit 14 and generating decoded signals; and a row decoder unit 18 for decoding signals received from the row predecoder unit 16 and generating signals WL less than 0:8191 greater than  to select word lines of the memory cell array unit 50.
The conventional semiconductor memory device further comprises: a command buffer unit 26 for receiving command signals i.e., row address strobe bar signal RASB, column address strobe bar signal CASB, write enable bar signal WEB, output enable bar signal OEB from external source(s); a command control unit 28 for receiving signals from the command buffer unit 26; and a test mode control unit 30 for receiving signals from the command control unit 28 and the address signals A less than 0:12 greater than  from the address buffer unit 10 and generating test mode signals TRATX, TRATY to detect deterioration in word lines and bit lines of the redundancy memory cell array unit 52.
The conventional semiconductor memory device further comprises: a row redundancy predecoder unit 20 for receiving row address data signals BXB less than 0:2 greater than  from the address buffer unit 14 and the test mode signals TRATX from the test mode control unit 30 and generating decoded signals TREB less than 0:7 greater than ; a row redundancy fuse unit 22 for generating signals REB less than 0:7 greater than  by programming row redundancy data; and a row redundancy enable signal generating unit 24 for receiving the decoded signals TREB less than 0:7 greater than  from the row redundancy predecoder unit 20 and the signals REB less than 0:7 greater than  from the row redundancy fuse unit 22 and generating signals RWL less than 0:7 greater than  to select word lines of the redundancy memory cell array unit 52.
The conventional semiconductor memory device further comprises: a column address buffer unit 32 for receiving address signals A less than 0:8 greater than  from the address buffer unit 10 and generating column address data signals BYB less than 0:8 greater than ; a column predecoder unit 34 for receiving column address data signals BYB less than 0:7 greater than  from the column address buffer unit 32 and generating decoded signals; and a column decoder unit 36 for receiving the decoded signals from the column predecoder unit 34, generating signals YS less than 0:255 greater than  to select bit lines of the memory cell array unit 50 and outputting the signals YS less than 0:255 greater than  to the sense amplification and I/O control unit 54.
The conventional semiconductor memory device still further comprises: a column redundancy predecoder unit 38 for receiving a column address data signal BYB less than 0 greater than  from the column address buffer unit 32 and the test mode signals TRATY from the test mode control unit 30 and generating decoded signals TYREB less than 0:1 greater than ; a column redundancy fuse unit 40 for generating signals YREB less than 0:1 greater than  by programming column redundancy data; and a column redundancy enable generating unit 42 for receiving the decoded signals TYREB less than 0:1 greater than  from the column redundancy predecoder unit 38 and the signals YREB less than 0:1 greater than  from the column redundancy fuse unit 40, generating signals RYS less than 0:1 greater than  to select bit lines of the redundancy memory cell array unit 52, and outputting the signals RYS less than 0:1 greater than  to the sense amplification and I/O control unit 54.
FIG. 2 is a circuit diagram of a part of the conventional row address buffer unit 14 for receiving the highest row address A less than 12 greater than  in FIG. 1. As shown in FIG. 2, the row address buffer unit 14 comprises: an inverter 141 for receiving signals BP4K outputted from a command decoder (not shown) in a refresh operation; an inverter 142 for inverting signals received from the inverter 141; an NMOS transistor Ni for discharging electric potential of a node Nd1 that receives the highest row address signal AK less than 12 greater than  from the address buffer unit 10 according to the signals received from the inverter 142 to the ground voltage Vss; a PMOS transistor P1 for transmitting a source voltage Vcc to a node Nd2 when the signal of the node Nd1 is at a low level; a PMOS transistor P2 connected to the PMOS transistor P1 in a row for applying the source voltage Vcc to its gate; NMOS transistors N2, N3 connected between the node Nd2 and the ground voltage Vss and their operation being controlled by signals of the source voltage Vcc and the node Nd1; an inverter 143 for inverting control signals XLAT; a clock inverter 144 for receiving signals of the node Nd2 according to the control signals XLAT being active at a high level in all operations except for refresh and outputting the inverted signals to a node Nd3; an inverter 145 for receiving signals of the node Nd3 and outputting the inverted signals to a node Nd4; an inverter 146 for receiving signals of the node Nd4 and outputting the inverted signals to the node Nd3; a clock inverter 148 for outputting the highest row address signal AR less than 12 greater than  received from the row address counter unit 12 to the node Nd3 according to control signal RLAT being active at a high level in a refresh operation; PMOS transistors P3, P4 connected between the source voltage Vcc and a node Nd5 in series and their operation being controlled by the ground voltage Vss and the node Nd4; an NMOS transistor N4 connected between the node Nd5 and a node Nd6 and its operation being controlled by signals of the node Nd4; an inverter 149 for receiving signals BP4K outputted from a command decoder (not shown) in a refresh operation and outputting the inverted signals; an inverter 150 for inverting and outputting signals received from the inverter 149; a NOR gate 151 for receiving signals received from the inverter 150 and the ground voltage Vss and outputting signals according to its NOR logic operation; a PMOS transistor P5 connected between the source voltage Vcc and the node Nd5 and for applying output signals of the NOR gate 151 to the gate; NMOS transistors N5, N6 connected between the node Nd5 and the ground voltage Vss in series and their operation being controlled by the ground voltage Vss and the output signals of the NOR gate 151; and an inverter 152 for inverting signals received from the node Nd5 and outputting them as the row address data signal BXB less than 12 greater than .
In the highest row address buffer having the above-mentioned structure, the signal BP4K outputted from the command decoder is at a low level, the control signal RLAT is at a low level and the control signal XLAT is at a high level in a normal operation, thereby latching the highest row address signal A less than 12 greater than  received from the address buffer unit 10 and outputting the latched signal as the highest row address data signal BXB less than 12 greater than .
On the other hand, in a 4K refresh operation, the signal BP4K outputted from the command decoder is at a high level, the control signal RLAT is at a high level and the control signal XLAT is at a low level. Therefore, in the 4K refresh operation, the highest row address buffer is not used since the electric potential of the node Nd1 for receiving the highest row address signal A less than 12 greater than  from the address buffer unit 10 is discharged to the ground Vss by the NMOS transistor N1, and the NMOS transistor N6 connected to the output terminal is turned off by the output signal of the NOR gate 151. At this time, the output signal BXB less than 12 greater than  of the highest row address buffer is at a low level.
In a 8K refresh operation, the signal BP4K outputted from the command decoder is at a low level, the control signal RLAT is at a high level and the control signal XLAT is at a low level. The highest row address signal AR less than 12 greater than  received from the row address counter unit 12 is transmitted to the node Nd3 through the clock inverter 148 operated by the high control signal RLAT. The highest row address signal AR less than 12 greater than  received from the row address counter unit 12 and transmitted to the node Nd3 is latched by the inverters 145, 146 and the latched highest row address signal AR less than 12 greater than  received from the row address counter unit 12 is outputted as the highest row address data signal BXB less than 12 greater than  through the output terminal.
FIG. 3 is a circuit diagram of the conventional row redundancy predecoder unit 20 in FIG. 1. As shown in FIG. 3, the row redundancy predecoder unit 20 includes: an inverter 204 for receiving a row address data signal BXB less than 0 greater than  received from the row address buffer unit 14 and outputting the inverted signal; an inverter 205 for inverting and outputting signals received from the inverter 204; an inverter 206 for receiving a row address data signal BXB less than 1 greater than  received from the row address buffer unit 14 and outputting the inverted signal; an inverter 207 for inverting and outputting the signal received from the inverter 206; an inverter 208 for receiving a row address data signal BXB less than 2 greater than  received from the row address buffer unit 14 and outputting the inverted signal; an inverter 209 for inverting and outputting the signal received from the inverter 208; a NAND gate 210 for receiving signals from the inverters 204, 206, 208 and outputting signals generated according to its NAND logic operation; a NAND gate 211 for receiving signals from the inverters 205, 206, 208 and outputting signals generated according to its NAND logic operation; a NAND gate 212 for receiving signals from the inverters 204, 207, 208 and outputting signals generated according to its NAND logic operation; a NAND gate 213 for receiving signals from the inverters 205, 207, 208 and outputting signals generated according to its NAND logic operation; a NAND gate 214 for receiving signals from the inverters 204, 206, 209 and outputting signals generated according to its NAND logic operation; a NAND gate 215 for receiving signals from the inverters 205, 206, 209 and outputting signals generated according to its NAND logic operation; a NAND gate 216 for receiving signals from the inverters 204, 207, 209 and outputting signals generated according to its NAND logic operation; a NAND gate 217 for receiving signals from the inverters 205, 207, 209 and outputting signals generated according to its NAND logic operation; an inverter 201 for receiving the test mode signal TRATX from the test mode control unit 30 and outputting the inverted signal; an inverter 202 for receiving the inverted signal from the inverter 201 and outputting the twice-inverted signal; and an inverter 203 for receiving and inverting the twice-inverted signal from the inverter 202 and outputting the three-times inverted signal.
The conventional row redundancy predecoder unit 20 further includes: a NOR gate 218 for receiving output signals from the NAND gate 210 and from the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 219 for receiving and inverting an output signal from the NOR gate 218 and outputting the inverted signal TREB less than 7 greater than ; a NOR gate 220 for receiving output signals from the NAND gate 211 and the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 221 for receiving and inverting an output signal from the NOR gate 220 and outputting the inverted signal TREB less than 6 greater than ; a NOR gate 222 for receiving output signals from the NAND gate 212 and from the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 223 for receiving and inverting an output signal from the NOR gate 222 and outputting the inverted signal TREB less than 5 greater than ; a NOR gate 224 for receiving output signals from the NAND gate 213 and from the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 225 for receiving and inverting an output signal from the NOR gate 224 and outputting the inverted signal TREB less than 4 greater than ; a NOR gate 226 for receiving output signals from the NAND gate 214 and from the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 227 for receiving and inverting an output signal from the NOR gate 226 and outputting the inverted signal TREB less than 3 greater than ; a NOR gate 228 for receiving output signals from the NAND gate 215 and the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 229 for receiving and inverting an output signal from the NOR gate 228 and outputting the inverted signal TREB less than 2 greater than ; a NOR gate 230 for receiving output signals from the NAND gate 216 and from the inverter 203 and outputting signals generated according to its NOR logic operation; an inverter 231 for receiving and inverting an output signal from the NOR gate 230 and outputting the inverted signal TREB less than 1 greater than ; a NOR gate 232 for receiving output signals from the NAND gate 217 and from the inverter 203 and outputting signals generated according to its NOR logic operation; and an inverter 233 for receiving and inverting an output signal from the NOR gate 232 and outputting the inverted signal TREB less than 0 greater than .
In the conventional row redundancy predecoder unit 20 having the above-mentioned structure, when the test mode signal TRATX generated at the test mode control unit 30 is active, one of output signals TREB less than 0:7 greater than  is selected at a low level by the row address data signals BXB less than 0:2 greater than  received from the row address buffer unit 14.
FIG. 4 is a circuit diagram of the conventional row redundancy enable signal generating unit 24 in FIG. 1. As shown in FIG. 4, the conventional row redundancy enable signal generating unit 24 includes: a NAND gate 241 for receiving the signal REB less than 7 greater than  from the row redundancy fuse unit 22 and the signal TREB less than 7 greater than  from the row redundancy predecoder unit 20; an inverter 242 for receiving and inverting an output signal from the NAND gate 241 and outputting the inverted signal; an inverter 243 for receiving and inverting an output signal from the inverter 242 and outputting an inverted signal RWL less than 7 greater than ; a NAND gate 244 for receiving the signal REB less than 6 greater than  from the row redundancy fuse unit 22 and the signal TREB less than 6 greater than  from the row redundancy predecoder unit 20; an inverter 245 for receiving and inverting an output signal from the NAND gate 244 and outputting the inverted signal; and an inverter 246 for receiving and inverting an output signal from the inverter 245 and outputting an inverted signal RWL less than 6 greater than . In the same manner, the other signals TREB less than 5 greater than  . . . TREB less than 0 greater than  and the other signals REB less than 5 greater than  . . . REB less than 0 greater than  are processed by the corresponding NAND gate and two inventers to output signals RWL less than 5 greater than  . . . RWL less than 0 greater than . For instance, a NAND gate 262 receives the signal REB less than 0 greater than  from the row redundancy fuse unit 22 and the signal TREB less than 0 greater than  from the row redundancy predecoder unit 20. An inverter 263 receives and inverts an output signal from the NAND gate 262 and outputs the inverted signal. Then an inverter 264 receives and inverts an output signal from the inverter 263 and outputs the inverted signal RWL less than 0 greater than .
The signals REB less than 0:7 greater than  received from the row redundancy fuse unit 22 become xe2x80x98lowxe2x80x99 when the row address signal applied externally is a row address signal necessary for redundancy and corresponds to data programming in the fuse. In a test mode, however, all of the signals REB less than 0:7 greater than  become xe2x80x98highxe2x80x99.
FIG. 5 is a circuit diagram of a part of the conventional column address buffer unit 32 in FIG. 1 for particularly illustrating a column address buffer that receives a column address signal A less than 8 greater than  from the address buffer unit 10. Although not shown, the column address buffer unit 32 further includes multiple buffers each having the same structure as shown in FIG. 5 and receiving and processing other column address signals A less than 0:7 greater than .
Referring to FIG. 5, the conventional column address buffer unit 32 comprises: a PMOS transistor P6 for transmitting a source voltage Vcc to a node Nd7 by a column address signal A less than 8 greater than  received from the address buffer unit 10; an inverter 321 for receiving and inverting a control signal YAEB and outputting the inverted signal; a PMOS transistor P7 for transmitting the source voltage Vcc to the node Nd7 by the signal received from the inverter 321; NMOS transistors N7, N8 connected between the node Nd7 and the ground voltage Vss in series and their operation being controlled by the output signal of the inverter 321 and the signal A less than 8 greater than  received from the address buffer unit 10; an inverter 322 for inverting a control signal YLB; a clock inverter 323 for transmitting the signal of the node Nd7 to a node Nd8 by a control signal YLB; an inverter 325 for receiving and inverting the signal of the node Nd8 and outputting the inverted signal to node Nd9; a clock inverter 326 for transmitting the signal of the node Nd9 to the node Nd8 by the control signal YLB; and an inverter 324 for receiving and inverting the signal of the node Nd8 and outputting the inverted signal BYB less than 8 greater than .
The control signal YAEB is a signal for controlling receipt of the column address signal A less than 8 greater than  from the address buffer unit 10. The control signal YLB becomes xe2x80x98lowxe2x80x99 in a column operation, thereby transmitting to the node Nd8 and latching the column address signal A less than 8 greater than  transmitted to the node Nd7.
FIG. 6 is a circuit diagram of the conventional column redundancy predecoder unit 38 in FIG. 1. As shown in FIG. 6, the column redundancy predecoder unit 38 comprises: an inverter 381 for receiving and inverting a signal BYB less than 0 greater than  from the column address buffer unit 32 and outputting the inverted signal; a NAND gate 383 for receiving signals from the inverter 381 and the test mode signal TRATY from the test mode control unit 30 and outputting signals generated according to its NAND logic operation; an inverter 384 for receiving and inverting an output signal from the NAND gate 383 and outputting the inverted signal; an inverter 385 for receiving and inverting a signal from the inverter 384 and outputting an inverted signal TYREB less than 0 greater than ; an inverter 382 for receiving and inverting an output signal from the inverter 381 and outputting the inverted signal; a NAND gate 386 for receiving an output signal from the inverter 382 and the test mode signal TRATY from the test mode control unit 30 and outputting signals generated according to its NAND logic operation; an inverter 387 for receiving and inverting an output signal from the NAND gate 386 and outputting the inverted signal; and an inverter 388 for receiving and inverting an output signal from the inverter 387 and outputting the inverted signal TYREB less than 1 greater than . When the test mode signal TRATY from the test mode control unit 30 is active, one of the outputted signals TYREB less than 0:1 greater than  becomes xe2x80x98lowxe2x80x99 according to the signal BYB less than 0 greater than  received from the column address buffer unit 32.
FIG. 7 is a circuit diagram of the conventional column redundancy enable signal generating unit 42 in FIG. 1. As shown in FIG. 7, the column redundancy enable signal generation unit 42 comprises: a NAND gate 421 for receiving the signal YREB less than 0 greater than  from the column redundancy fuse unit 40 and the signal TYREB less than 0 greater than  from the column redundancy predecoder unit 38; an inverter 422 for receiving and inverting an output signal from the NAND gate 421 and outputting the inverted signal; an inverter 423 for receiving and inverting an output signal from the inverter 422 and outputting the inverted signal RYS less than 0 greater than ; a NAND gate 424 for receiving the signal YREB less than 1 greater than  from the column redundancy fuse unit 40 and the signal TYREB less than 1 greater than  from the column redundancy predecoder unit 38; an inverter 425 for receiving and inverting an output signal from the NAND gate 424 and outputting the inverted signal; and an inverter 426 for receiving and inverting an output signal from the inverter 425 and outputting the inverted signal RYS less than 1 greater than .
The signals YREB less than 0:1 greater than  received from the column redundancy fuse unit 40 become xe2x80x98lowxe2x80x99 by data programming in fuse. Here, the signals YREB less than 0:1 greater than  become xe2x80x98lowxe2x80x99 when the column address signal applied externally is a column address signal necessary for redundancy and corresponds to data programming in the fuse. In a test mode, however, all of the signals YREB less than 0:1 greater than  become xe2x80x98highxe2x80x99.
The operation of the conventional semiconductor memory device having the above-mentioned structure will be described in more detail as follows.
In order to use redundancy memory cells provided in a redundancy region of the memory device, it is first required to detect deterioration of redundancy memory cells. If there is no deterioration or damage to the redundancy memory cells, the redundancy memory cells will replace defective memory cells. The test operation to detect any deterioration in the redundancy memory cells starts when a test mode signal TRATX becomes active and involves detection of any deterioration of word lines in the redundancy memory cell array unit 52.
The test mode signal TRATX is generated by a combination of the address signals A less than 0:8 greater than  received from the address buffer unit 10 and the signal received from the command control unit 28 in the test mode control unit 30, and is applied to the row redundancy predecoder unit 20.
The row redundancy predecoder unit 20 outputs one of 8 output signals TREB less than 0:7 greater than  as a xe2x80x98lowxe2x80x99 level signal based on the test mode signal TRATX received from the test mode control unit 30 and the row address data signals BXB less than 0:2 greater than  received from the row address buffer unit 14. Here, the operation that a xe2x80x98lowxe2x80x99 signal is generated from the row redundancy predecoder unit 20 corresponds to the operation that redundancy cells are selected instead of the defective cells in a normal operation mode. And, the defects of word lines are detected by accessing the redundancy cell array. In a normal operation, a signal for selecting redundancy memory cells by fuse data is one of signals REB less than 0:7 greater than  outputted from the row redundancy fuse unit 22 that becomes xe2x80x98lowxe2x80x99.
The test operation to detect a deterioration of bit lines of the redundancy cell array unit 52 is performed by applying the test mode signal TRATY to the column redundancy predecoder unit 38.
FIG. 8 is an operation timing for detecting deterioration of redundancy memory cells by using the conventional semiconductor memory device having the redundancy circuit as discussed above. In FIG. 8, t0 represents a time when a normal operation is performed, t1 represents a time for precharging all memory cells, t2 represents a time for entering into the test mode by application of particular commands and addresses, t3 represents a time for activating the test mode signal TRATX or TRATY for redundancy memory cell test, t4 represents a time for testing deterioration of redundancy memory cells, t5 represents a time for exiting the test mode, t6 represents a time for precharging all memory cells, t7 represents a time for applying a particular command for a normal operation, and t8 represents a time for performing a normal operation instead of the test mode operation.
However, the conventional semiconductor memory device having the redundancy circuit has at least several drawbacks. First, a word line disturb test mode is a mode for testing the interference effect of all word line operations by fixing all bit lines (bit line addresses) and is essential to detecting deterioration of memory cells. The necessary time for the word line disturb test mode will be represented in EQUATION 1.
tWRITE+tDISTURB+tSCAN+tREAD=(tcyclexc3x97Nredxe2x80x94memory)+(trefreshxc3x97Nword)+(tcyclexc3x97Nword2)+(tcyclexc3x97Nredxe2x80x94memory)xe2x80x83xe2x80x83[EQUATION 1]
In EQUATION 1 above, xe2x80x9ctWRITExe2x80x9d is a time necessary for a write operation, and xe2x80x9ctcyclexe2x80x9d is a time necessary for turning off the word lines, after driving the word lines of memory cells and performing one read or write operation. xe2x80x9ctcyclexe2x80x9d is also referred to hereinafter as xe2x80x9cword line move timexe2x80x9d. Generally, the word line move time is 100 ns. xe2x80x9cNred_memoryxe2x80x9d is the number of redundancy memory cells and xe2x80x9ctDISTURBxe2x80x9d is a time necessary for being influenced by all the word lines xe2x80x9cNwordxe2x80x9d including tested word lines of the memory cells, corresponding to continuous on/off time during a refresh time xe2x80x9ctrefreshxe2x80x9d (generally 64 msec) to all word lines. xe2x80x9ctSACNxe2x80x9d is an operation signal for refreshing all the word lines in order to maintain data of the memory cells connected to unselected word lines. The refresh operation is expressed by xe2x80x9cNword2xe2x80x9d. The xe2x80x9ctREADxe2x80x9d is a time necessary for performing a read operation.
The test time T of normal memory cell regions is represented in EQUATION 2. In this equation, xe2x80x9cNmemoryxe2x80x9d indicates the entire normal memory cell area.
T=(tcyclexc3x97Nmemory)+(trefreshxc3x97Nword)+(tcyclexc3x97Nword2)+(tcyclexc3x97Nmemory)xe2x80x83xe2x80x83[EQUATION 2]
As an example, when a redundancy memory cell having 8 word lines and 2 column lines is connected to a normal memory cell of 64M bit having 8192 word lines, and 4 bit lines are connected to 1 column line comprising 16 I/O lines, Nred_memory is 1024 bit. Here, the Nred_memory having 1024 bit needs the test time of approximately 531 sec. according to EQUATION 1 above. The time for testing normal memory cells is also determined to be 537.7 sec. and EQUATIONs 1 and 2 have an approximate value by a multiplication xe2x80x98trefreshxc3x97Nwordxe2x80x99. This is because word lines having redundancy memory cells connected thereto correspond to the number of word lines of normal memory cells and therefore, a disturb operation time is necessary for all word lines. That is, there is a problem in that the test time for redundancy memory cells is similar to that for normal memory cells although the number of redundancy memory cells is smaller than the number of normal memory cells.
Second, there is still a problem in that there remains deterioration that is not detected by testing of the redundancy memory cells. That is, in the conventional test mode for detecting redundancy memory cells, redundancy memory cell blocks are detected by performing a test mode after detecting the normal memory cells and therefore, any deterioration generated at the interface of redundancy memory cells adjacent to the normal memory cells is not tested due to the time lapse of several msec. Therefore, certain defective memory cells are substituted with those redundancy memory cells having deteriorations. This causes a problem of recovery failures and deterioration in device performance.
Accordingly, the present invention has been made to solve the above-mentioned problems and other problems associated with conventional art.
An object of the invention is to provide a redundancy method for semiconductor memory device, capable of detecting deterioration by interference of memory cells adjacent to a normal memory cell with a redundancy memory cell while reducing the detection time.
Another object of the present invention is to provide a semiconductor memory device having a redundancy circuit capable of realizing a redundancy method of the present invention.
In order to achieve the above and other objects, a semiconductor memory device according to an embodiment of the present invention comprises a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the redundancy memory cell array unit and the adjacent normal memory cell immediately after a word line move time xe2x80x98tcyclexe2x80x99 in the normal memory cell array unit by using address data.
The memory driving unit according to an embodiment of the present invention comprises: a test mode signal generating unit for generating a test mode signal to indicate a test operation; a row address counter unit for receiving the test mode signal, a first signal enabled in a refresh mode and a second signal toggling in the refresh mode and for generating a row address counter signal; a row counter reset unit for receiving the test mode signal, the second signal and a part of the row address counter signal and for generating a reset signal to reset the row address counter unit; a row counter reset initializing unit for receiving the test mode signal and for generating an initialization signal to initialize the row counter reset unit; a row address buffer unit for receiving the row address counter signal and a row address signal from an external source and for generating a row address data signal; a row predecoder and a decoder unit for receiving the row address data signal and for generating a signal to select word lines of the normal memory cell array unit; a row redundancy address buffer unit for receiving the highest row address signal received from an outside source, the test mode signal and the row address counter signal and for generating a row redundancy address signal; a row redundancy predecoder and decoder unit for receiving the row address data signal, the test mode signal and the row redundancy address signal and for generating a signal to select word lines of the redundancy memory cell array unit; a column address buffer unit for receiving a column address signal from an external source and for generating a column address data signal; a column predecoder and decoder unit for receiving the column address data signal and for generating a signal to select word lines of the normal memory cell array unit; a column redundancy address buffer unit for receiving the highest column address signal received from an external source and the test mode signal and for generating a column redundancy address signal; and a column redundancy predecoder and decoder unit for receiving the column address data signal, the test mode signal and the column redundancy address signal and for generating a signal to select redundancy word lines of the redundancy memory cell array unit.
A semiconductor memory device according to another embodiment of the present invention comprises: a normal memory cell array unit comprising N memory banks for storing a plurality of data; a redundancy memory cell array unit comprising N memory banks for recovering defective cells of the normal memory cell array unit; a test mode signal generating unit for generating a test mode signal to indicate a test operation; a row address counter unit for receiving the test mode signal, a first signal enabled in a refresh mode and a second signal toggling in the refresh mode and for generating a row address counter signal; a row counter reset unit for receiving the test mode signal, the second signal and a part of the row address counter signal and for generating a reset signal to reset the row address counter unit; a row counter reset initializing unit for receiving the test mode signal and for generating an initialization signal to initialize the row counter reset unit; a row address buffer unit for receiving the row address counter signal and a row address signal from an outside source and for generating a row address data signal; N row predecoder and decoder units for receiving the row address data signal and for generating a signal to select word lines of the normal memory cell array unit; a row redundancy address buffer unit for receiving the highest row address signal, the test mode signal and the row address counter signal and for generating a row redundancy address signal; N row redundancy predecoder and decoder units for receiving the row address data signal, the test mode signal and the row redundancy address signal and for generating a signal to select redundancy word lines of the redundancy memory cell array unit; a column address buffer unit for receiving a column address signal from an external source and for generating a column address data signal; N column predecoder and decoder units for receiving the column address data signal and for generating a signal to select word lines of the normal memory cell array unit; a column redundancy address buffer unit for receiving the highest column address signal received from an external source and the test mode signal and for generating a column redundancy address signal; N column redundancy predecoder and decoder units for receiving the column address data signal, the test mode signal and the column redundancy address signal and for generating a signal to select redundancy word lines of the redundancy memory cell array unit; a band address buffer unit for receiving an address signal having address data of a memory bank; and a bank control units for selectively controlling operations of the N row predecoder and decoder unit, the N row redundancy predecoder and decoder units, the N column predecoder and decoder units, and the N column redundancy predecoder and decoder units by decoding address signals received from the bank address buffer unit in the test mode.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.